仪表放大器
共栅
电源抑制比
直接耦合放大器
放大器
运算跨导放大器
电子工程
运算放大器
电气工程
计算机科学
全差分放大器
共模抑制比
射频功率放大器
CMOS芯片
工程类
作者
H. K. Yogitha,Karade Sinchana,Shristi Biyani,Rashmi Seethur
标识
DOI:10.1109/icsima59853.2023.10373502
摘要
This paper deals with the design of an instrumentation amplifier (INA) featuring a folded cascode amplifier in the output stage. Instrumentation amplifiers play a pivotal role in various applications, particularly in biomedical amplifiers and audio instrumentation systems, where they excel at capturing signals amidst significant noise. By incorporating the folded cascode amplifier, this design ensures both high gain and high output voltage swing, all while maintaining lower power consumption. The proposed design comprises a two-stage operational amplifier (op-amp) in the input stage, complemented by a folded cascode stage amplifier in the output stage. The design process begins with an explanation of the designs of the two-stage op-amp and folded cascode amplifier followed by a comparison of their results. Finally, an instrumentation amplifier integrating both are designed and analyzed. This work is designed and simulated for 90nm CMOS Technology on Cadence Virtuoso with a 1.2V power supply and input common mode voltage of 800mV. Overall, the designed INA achieves an optimal gain of 47.7dB along with CMRR (Common Mode Rejection Ratio) of 98.25dB and PSRR (Power Supply Rejection Ratio) of 109.4dB with a bandwidth of 1.25MHz. The total power consumed by the instrumentation amplifier is 317µW with an input referred noise of 1.89µV/√Hz which is suitable for the above-stated applications.
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