Advanced Co-packaged Optics (CPO) Solutions and Technology Challenge for Silicon Photonics Applications

Major semiconductor market applications require HPC, Cloud, Autonomous Car and Generative AI to get better daily life. When large scale expansion requirement from each application, we will receive a large amount of data which will be generated in the computing process by efficiently transmitted, calculated and stored. In recent years, the demand for data transmission in large data centers and cloud servers. Industrial networking countries have been driving into the optical communication field, by using "optical light" instead of "electrical" as the carrier during data transmission. The major benefits for optical communications can improve the transmission capacity, bandwidth, power efficiency to increase data bandwidth and reduce electricity energy consumption. However, the current networking servers are using the traditional pluggable transceiver method, but power consumption is a major concern. In order to overcome these challenges and achieve higher bandwidth and faster data processing needs, a "Co-packaged Optical" (CPO) packaging solution was developed to improve power and better bandwidth. The CPO product combined EIC (Electronic Integrated Circuit) and PIC (Photonic Integrated Circuit) with optical waveguides design into OE (Optical Engine) module and integrated switch chips and multiple OE modules into single package integration. In this paper, we see different OE structures (EIC/PIC) by horizontal and vertical integration methodologies, and use fan-out embedded with RDL, 3D TSV die stacking and hybrid bonding technologies to integrate EIC/PIC function into OE module. The FAU (fiber array unit) will use optical passive/active alignment method to put on a waveguide area of PIC with grating coupling (GC) and edge coupling (EC) solutions. Both electrical performance and thermal performance are major challenges for OE solutions. Compared with electrical performance by insertion loss and verify heat sink warpage performance simulation comparison. We also demonstrated the Fan-out CPO (FO-CPO) structure warpage challenge and assembly solutions during wafer level bonding and package level bonding to get better warpage control result. Finally, this paper will provide the advanced CPO and OE technology solutions for the next generation networking and HPC markets.