SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification

Simulation-based verification of Very-Large-Scale Integration (VLSI) chip design is inevitable. However, the simulation speed can be a bottleneck in the verification process productivity. People tried to accelerate simulation-based verification through parallelization, emulation, and reducing the number of test scenarios, etc. In this paper, we exploited the power of abstraction of SystemC to design fast and accurate golden functional reference models. These reference models can be integrated in the Universal Verification Methodology (UVM) based TestBench through Transaction Level Modeling (TLM). Thus, the UVM based TestBench interacts with the SystemC reference model to get the golden values, and use them for checking. We used the proposed methodology to verify the execution unit (EXU) of the open-source RISC-V based VeeR EL2 processor core. The experimental results showed that the proposed TestBench architecture with SystemC reference model is up to 15x faster than the TestBench with SystemVerilog reference model.