Ultra-low power magneto-elastic analog-to-digital converter based on magnetic tunnel junctions and bicomponent multiferroic nanomagnet

<sec>In recent years, the utilization of artificial intelligence and big data has led to the rise of compute-in-memory signal processing as the primary method for ADC design. Spintronic memory devices, which have non-volatile and low static power consumption characteristics, are particularly suitable for the design of low-power, high-bandwidth compute-in-memory ADCs.</sec><sec>In this paper, a 3-bit magneto-elastic analog-to-digital converter (MEADC) is proposed, which comprises eight magnetic tunnel junctions (MTJs), where the MTJ free layer is a bicomponent multiferroic nanomagnet. The bicomponent multiferroic nanomagnet can attain deterministic magnetization switching under zero-field condition by regulating the strain-mediated voltage. It has been discovered that there is a linear correlation between the thickness of the piezoelectric layer and the critical flip voltage in a bicomponent multiferroic nanomagnet of a given size and material. Using this principle, the thickness of the piezoelectric layer is adjusted to allow the MEADC to have eight different voltage switching thresholds. This can make the analog signal converted into a combination of different magnetization states of eight multiferroic MTJ. A latch comparator and an independent read circuit are designed to detect the MTJ’s resistance state output a digital signal. Monte Carlo simulations indicate that the MEADC can achieve a 100% success rate of writing at room temperature. Additionally, the read circuit and write circuit are separated from each other, thus the same reference voltage can be set for each MTJ and result in higher readability. Micromagnetic simulation and numerical analysis demonstrate that the MEADC can operate at a maximum frequency of 250 MHz, and the energy consumption of a single conversion is only 20 aJ. Compared with the magnetic analog-to-digital converter based on the Racetrack technology, the energy consumption is reduced by 1000 times, and the sampling rate is increased by 10 times. The MEADC proposed in this paper offers an essential technical support for the spintronics-based compute-in-memory integrated circuit architecture.</sec>