X64 UCIe Chiplet Interconnection at 32 GT/s on a Silicon Core Substrate

For the first time, we demonstrate the integration of an X64 UCIe interface directly onto a silicon core substrate, eliminating the need for a silicon or RDL interposer. The UCIe specification defines chiplet interconnect protocols across various levels, and our work targets the highest density and speed. Our implementation achieves unidirectional communication at 32 GT/s with 64 Tx and 64 Rx signals, adhering to a bump pitch of 55 μm, a module depth of 1585 μm, and a maximum trace length of 2 mm. We successfully implemented the highest-bandwidth X64 UCIe on a Si-core substrate and validated its performance through extensive simulations, ensuring compliance with UCIe standards. Traditionally, such connections require a silicon interposer mounted on a laminate substrate in a 2.5D integration approach. However, this method introduces additional interconnect layers, parasitics, and cost constraints while limiting interposer size. Our results demonstrate that a single silicon core substrate can effectively replace both the laminate and Si interposer, enabling direct UCIe routing with improved performance and efficiency.