Blocking transition of interface traps in MoS2/SiO2 field-effect transistors

The interface traps and associated charge disorder in two-dimensional-material field-effect transitors (FETs), and many other devices, limits their performance but offers interesting physics and potential for applications. The electrical conductivity with gate-sweep in a few-layer ${\mathrm{MoS}}_{2}$-on-${\mathrm{SiO}}_{2}$ FET is found to show an abrupt reduction in hysteresis when cooled. The hysteresis and time-dependent conductivity of the ${\mathrm{MoS}}_{2}$ channel are modeled using the dynamics of interface traps' occupancy. The reduction in hysteresis is found to be steepest at a blocking temperature near 225 K. This is attributed to the interplay between thermal and barrier energies and fitted using a distribution of the latter. Further, the charge stored in the blocked traps at low temperature, and thus the threshold gate voltage, is reversibly programed over a wide range by cooling under suitable gate voltage. This illustrates the application of this blocking of traps for heat-assisted nonvolatile memory.