GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

Abstract For the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript. SE‐GAA‐TFET is found to exhibit improved performance in terms of various analog/RF and DC parameters. As channel/source (C/S) interface and electric field exerted by gate are perpendicular to each other, radius of channel is downscaled to enhance electric filed, without reducing area of the tunneling. Furthermore, the presence of GaSb/GaAs heterojunction at C/S interface leads to reduction in the effective band overlap, which helps a great number of mobile charges to tunnel through C/S boundary at ON‐state. The consequences of variation in different geometrical metrics are evaluated to optimize the device performance. SE‐GAA‐TFET is found to offer a current switching ratio (CSR) of ~10 13 along with 32.2 mV dec −1 of average sub‐threshold swing (SS AVG ). Furthermore, improvement in transconductance and parasitic capacitance boost the cut‐off frequency of SE‐GAA‐TFET up to 37 GHz. Next, both positive and negative traps are introduced at S/C interface and the study reveals that there is no much deviation in parameters of the transfer characteristics like I ON , SS AVG , and I OFF of SE‐GAA‐TFET. Next, proper benchmarking is done to compare the performance of the SE‐GAA‐TFET with similar devices available in literature and it is found that proposed SE‐GAA‐TFET exhibits better DC performance due to improved electrostatic behavior. Finally, SE‐GAA‐TFET is found to offer better fall time along with full‐voltage swing when deployed in a resistive load inverter.