SiC MOSFET threshold voltage stability during power cycling testing and the impact on the result interpretation

The gate-oxide processing for SiC MOSFET devices is challenging and can lead to pronounced trapping effects at the $\mathbf{SiC}/\mathbf{SiO}_{2}$ interface, which then can induce threshold voltage instabilities during switching and other long-term tests. This effect can influence the $\mathbf{R_{DS, on}}$ , if the channel is not completely closed, and also the temperature determination by the $\mathbf{V}_{\mathbf{S}\mathbf{D}}(\mathbf{T})$ method. This paper presents a special measurement circuit for a live threshold voltage measurement during power cycling to study these issues during lifetime testing. The influence on the lifetime determination during power cycling is evaluated and can be in parts neglected for state-of-the-art devices. Even though high temperatures are present, the number of power cycles and respectively the time under a certain gate voltage is not sufficient to induce a reasonable gate threshold shift. For the investigated devices a negative influence on the lifetime testing and results interpretation can hence be ruled out.