Electrical impedance imaging system using FPGAs for flexibility and interoperability

计算机科学 现场可编程门阵列 嵌入式系统 灵活性(工程) 互操作性 模块化设计 计算机硬件 软件
作者
Harsh Sohal,Hun Wi,Alistair McEwan,Eung Je Woo,Tong In Oh
出处
期刊:Biomedical Engineering Online [Springer Nature]
卷期号:13 (1): 126-126 被引量:11
标识
DOI:10.1186/1475-925x-13-126
摘要

Modern EIT systems require simultaneously operating multiple functions for flexibility, interoperability, and clinical applicability. To implement versatile functions, expandable design and implementation tools are needed. On the other hand, it is necessary to develop an ASIC-based EIT system to maximize its performance. Since the ASIC design is expensive and unchangeable, we can use FPGAs as a prior step to the digital ASIC design and carefully classify which functions should be included in the ASIC. In this paper, we describe the details of the FPGA design adopted in the KHU Mark2.5 EIT system. We classified all functions of the KHU Mark2.5 EIT system into two categories. One is the control and processing of current injection and voltage measurement. The other includes the collection and management of the multi-channel data with timing controls for internal and external interconnections. We describe the implementation of these functions in two kinds of FPGAs called the impedance measurement module (IMM) FPGA and the intra-network controller FPGA. We present functional and timing simulations of the key functions in the FPGAs. From phantom and animal imaging experiments, we show that multiple functions of the system are successfully implemented in the FPGAs. As examples, we demonstrate fast multi-frequency imaging and ECG-gated imaging. Given an analog design of a parallel EIT system, it is important to optimize its digital design to minimize systematic artifacts and maximize performance. This paper described technical details of the FPGA-based fully parallel EIT system called the KHU Mark2.5 with numerous functions needed for clinical applications. Two kinds of FPGAs described in this paper can be used as a basis for future EIT digital ASIC designs for better application-specific human interface as well as hardware performance.
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