RISC-V processor-based automatic access floating-point computing accelerated dataflow co-processor

The Von Neumann and Harvard architectures are very efficient as the common structures of modern computers. However, they reach certain bottlenecks in parallelism, access speed, and power. In this paper, we propose a new architecture to further improve the parallelism and access speed of RISC-V computing system by adding data flow co-processors. The data flow coprocessor in the architecture is further optimized according to the computational characteristics of modern convolutional neural networks. The computation speed of floating- point numbers is increased to further improve the usefulness of the architecture. The data flow coprocessor adds an automatic access mechanism to further relieve the computational pressure on the main processor. Finally, experiments are conducted on the structure with the NEXYS A7 100t FPGA development board to verify the feasibility of the system.