Building Hardware Security Primitives Using Scan-based Design-for-Testability

Scan chain is typically used to provide test engineers with complete controllability and observability to the circuit under test to reduce the complexity of VLSI testing. However, it should not be dismissed as just a one-hit-wonder that merely facilitates the test of digital circuits. This study presents a comprehensive review of the recent proposals on how scan chain design can present its versatility as security primitives in different areas of hardware security. More specifically, we elaborate its usage in hardware intellectual property watermarking, fingerprinting, and metering, as well as in the design of physical unclonable functions and counterfeit detection. We analyze the challenges and opportunities in building hardware security primitives using modern scan-based design-for-testability (DfT).