SOI pMOS drain leakage understanding based on TCAD and measurements

This work investigates Silicon-on-Insulator (SOI) pMOS drain leakage current. 2D TCAD simulations with Schenk band-to-band tunneling and Field-Enhanced SRH generation recombination models reproduce experimental leakage for various biases and temperatures (25 to 125°C). Furthermore, we demonstrate that leakage variation with channel thickness is due to carrier lifetime variation. Experimentally, working on the lightly doped drain (LDD) to channel junction (position, steepness and dopants level) results in a leakage modulation for high electric field only. This behavior is perfectly reproduced by TCAD, enabling predictive work about leakage current optimization.