无杂散动态范围
比较器
逐次逼近ADC
电子工程
计算机科学
电容器
动态范围
转换器
抖动
偏移量(计算机科学)
放大器
电压
CMOS芯片
电气工程
工程类
噪声整形
程序设计语言
作者
Jie Sun,Minglei Zhang,Lei Qiu,Jianhui Wu,Weiqiang Liu
出处
期刊:IEEE Transactions on Very Large Scale Integration Systems
[Institute of Electrical and Electronics Engineers]
日期:2020-04-01
卷期号:28 (4): 1074-1078
被引量:12
标识
DOI:10.1109/tvlsi.2019.2961149
摘要
This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.
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