A Comprehensive Wafer Level Reliability Study on 65nm Silicon Interposer

Stacking of chips vertically will reduce the interconnection resistance and as a result enhance data communication between chips. Memory chip to logic chip integration requires close proximity to improve the performance and is an alternate to SOC type chip level integration. Memory to logic integration can be done side by side using a silicon interposer, known as 2.5D integration. Copper filled through Silicon via (TSV) in a silicon wafer is the key enabling technology for this integration. In this paper 100um thin silicon interposer is fabricated with a 3 BEOL (Back end of line) metal process having TSV with 10um diameter. A standard interposer and a stitched interposer reliability challenges are described in this paper. Wafer level reliability of the interposer is studied with electromigration and stress-migration.