Design and Realization of RS Encoder Based on FPGA

By analyzing and researching the RS encoder in communication system,it is found the problems of complex circuit structure and low processing speed occurred to traditional RS encoder.Focused on the problems,a new encoder construction method was proposed.A RS(255,223) encoder with symmetric coefficients of generator polynomial was implemented under the Quartus7.0,and test,simulation and validation were conducted under Matlab and ModelSim.The simulation result indicates that the performance of the encoder is better,and the encoder is featured with high speed and low hardware complexity.