Thermal stresses around TSV structure in stacked Si chips

Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate. It is difficult to correspond to downsizing and high-performing of electronic devices because that large area is occupied by the package. The semiconductor chips have been stacked and TSVs have been used to communicate between the chips in order to solve above problems. The 3D stacked structure which was developed by ASET (Association of Su per-Advanced Electronics Technologies) [10] is shown in Fig.1. TSV (copper) is electrode which passes through silicon chip and micro bump (copper) [11] is arranged between chips. Heat is generated in package due to operation of semiconductor device, and it has been reported that silicon is broken by thermal stress which is depend on temperature increment. In case of 3D-SÌP, higher stress has to be considered in the most outer part of TSV and micro bump structure due to warp and mismatch of CTE (coefficient of thermal expansion) of material. Therefore simulations with detail model must be desired for more accurate evaluation of stresses in Si chips and TSVs. However it is difficult that all of TSVs and micro bumps in chips were modeled due to large number of numerical data even if the latest computing systems have been adopted.