CoWoS Architecture Evolution for Next Generation HPC on 2.5D System in Package

Chip-on-wafer-on-substrate (CoWoS®) is an advanced packaging technology to make high performance computing (HPC) and artificial intelligence (AI) components. As a high-end system-in-package (SiP) solution, it enabled multi-chip integration in a side-by-side manner within a compact floor plan than traditional multi-chip module (MCM). Scaling up of the interposer area is one of the key attributes to accommodate more active circuits and transistors into the package to boost the SIP system performance. CoWoS-S based on Si interposer has been developed up to an interposer area of 2500 mm ² by four-mask stitching. However, the unprecedented interposer area poses major yield and manufacturing challenges. Ways to overcome the Si interposer size limitation becomes highly desirable. In this paper, we introduce CoWoS-L, a new architecture in the CoWoS family, to address the large Si interposer defect-driven yield loss concern. The interposer of CoWoS-L includes multiple local Si interconnect (LSI) chip lets and global redistribution layers (RDL) to form a reconstituted interposer (RI) to replace a monolithic silicon interposer in CoWoS-S. The LSI chiplet inherits all the attractive features of Si interposer by retaining sub-micron Cu interconnects, through silicon vias (TSV), and embedded deep trench capacitor (eDTC) to ensure good system performance, while avoids the issues associated with one large Si interposer, such as yield loss. Furthermore, through insulator via (TIV) is introduced in the RI as vertical interconnect to provide a low insertion loss path than TSV. CoWoS-L with 3x reticle size (~2500 mm2) interposer carried multiple SoC/chiplet dies and 8 HBMs has been successfully demonstrated. The electrical characteristics and component level reliability are reported. The stable reliability results and excellent electrical performance indicate that the CoWoS-L architecture will continue the scaling momentum of CoWoS-S to meet the demand of future 2.5D SiP systems for HPC and AI deep learning.