2024 IEEE International Reliability Physics Symposium (IRPS 2024)

30 a.m.TUT9 (Tutorial) -Reliability of Nanoelectronics Based on Two-Dimensional Materials, Theresia Knobloch; TU Wien Two-dimensional (2D) materials possess various intriguing properties, making them promising building blocks for future nanoelectronics.For example, 2D semiconductors offer sizable mobilities and high on-currents in thin layers, allowing for excellent gate control in scaled transistors.Nonetheless, to bridge the gap between current device prototypes and commercial applications, multiple challenges must be overcome, including identifying gate stacks that are both scalable and allow for reliable operation throughout the device's lifetime.Tutorial 10 Monday, April 15, 08:30 a.m.-10:00 a.m.PDT Venue: Int.III & IV 08:30 a.m.TUT10 (Tutorial) -SiC Device Reliability and Failure Analysis, Donald Gajewski; Wolfspeed, Inc.In this tutorial, I will give a brief introduction to reliability and failure analysis fundamentals; review key reliability aspects for SiC devices such as bias temperature instability, bipolar stability due to Shockley stacking faults, gate oxide reliability, humidity effects, reverse bias, single event burnout and power cycling; illustrate mission profile analysis techniques; review essential failure analysis techniques such as fault detection, FIB/SEM and EBIC; and review the latest industry consortia standards and guidelines.Tutorial 11 Monday, April 15, 08:30 a.m.-10:00 a.m.PDT Venue: Cap Rock I, II & III 08:30 a.m.TUT11 (Tutorial) -Interconnect Reliability for Chip Design, Baozhen Li; IBM Infrastructure Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications.For high end and critical application products, reliability co-optimization is an important integral part of DTCO.This tutorial focus on the interconnect reliability optimization considerations for chip design.Discussions will be made from understanding the intention and limitation of various design guidelines & reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.Tutorial 12 Monday, April 15, 08:30 a.m.-10:00 a.m.