计算机科学
算法
汉明码
汉明距离
编码(社会科学)
代码字
解码方法
数据压缩
编码(内存)
位(键)
错误检测和纠正
二进制代码
数学
块(置换群论)
格雷码
区块代码
编码(集合论)
误码率
作者
Usha S. Mehla,Kankar S. Dasgupta,Niranjan M. Devashrayee
出处
期刊:International Conference on VLSI Design
日期:2010-01-03
卷期号:: 33-38
被引量:23
标识
DOI:10.1109/vlsi.design.2010.18
摘要
Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in past. Run Length Coding is one of the most familiar coding methodologies for compression. In this paper, we present a new scheme named Hamming Distance Based Reordering and Column wise Bit Stuffing with Difference Vector (HDR-CBS-DV), which can be used with any run length based code technique for better compression ratio. Four techniques have been applied in this scheme: Selection of first vector, Hamming Distance Based Reordering, Columnwise Bit Stuffing and Difference Vector. Instead of directly applying any known run length code like Golomb, Frequency Directed Run Length (FDR), Extended FDR (EFDR), Modified FDR (MDFR) or Shifted Alternate FDR (SAFDR) to given test set, if we apply the proposed scheme to test set prior to applying the run length base code, the compression obtained is improved drastically. The experimental results on ISCAS89 Benchmark circuits shows that the test data compression ratio improves significantly for each case. It is also noteworthy that in most of the case, this scheme does not involve any extra silicon area over-head compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. The proposed scheme can be easily integrated into the existing industrial flow.
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