Patterning half-wavelength DRAM cell using chromeless phase lithography (CPL)

For each generation of DRAM cell layout design to achieve ever higher device density packing, tighter pitched array cell patterns are required. Very tight-pitched patterns present a great imaging challenge for sub-100nm devices. In order to pattern the cell patterns using KrF exposure, it is necessary to make use of resolution enhancement techniques (RET) such as phase shifting mask (PSM), off-axis illumination (OAI), and optical proximity correction (OPC). At k₁ approximately 0.3 imaging, we have found a combination of PSM, OAI, and OPC that allows the most robust manufacturing process. In this paper, we have applied chromeless phase lithography (CPL) with OPC on the critical DRAM cell layers, such as capacitor node and contacts. The methodology of manipulating CPL image contrast by using phase cancelling effect is proposed. The mask design flow are discussed along with the consideration of data preparation and mask manufacturing complexity for CPL. The patterning performance has been characterized by using both simulation and experimental data from printed resist wafer. Using CPL mask with optimized OAI, a 0.8 NA 248nm exposure system is well capable of printing sub-100nm DRAM cell patterns.