Simulations of variable I-layer thickness effects on silicon PIN diode I-V characteristics

PIN Diode gains its name from the idealized intrinsically doped, I-layer, sandwiched between a P-type and N-type layer. The N-layer of PIN diode was doped with Arsenic and the P-layer doped with Boron. The performance of the PIN diode primarily depends on the chips geometry and the nature of the semiconductor material, particularly in the I-layer. This paper presents a simulation of four I-layer thickness (5μm, 20μm, 30μm and 50μm) effects on the silicon PIN diode I-V characteristics carried out by using Sentaurus Technology Computer Aided Design (TCAD). The major goals of the simulation work are to study the I-layer thickness (d) effects on diode I-V characteristics and to implement PIN diode fabrication process flow into a commercially available process environment. The important parameters of PIN diode were analyzed to study the effect of PIN diode I-V characteristics.