32.2 A PVT-Robust Frequency-Scalable Fully Dynamic ΔΣ ADC with Bottom-Plate Level Shift

A fully dynamic calibration-free$\Delta \Sigma$ADC using capacitive-degeneration integrators with bottom-plate level shift (BPLS) is presented. BPLS samples negative charge to reduce threshold-voltage dependence, improve settling, and cancel kT/C noise, enabling 0.5pF sampling capacitance. The ADC achieves 91.7dB peak SNDR and 95.6dB DR with$10.1 \mu \mathrm{W}$at 10kHz bandwidth (BW). Up to 40kHz BW, the worst-case DR degradation is$\leq 2 \text{dB}$under$\pm 10 \% \mathrm{V}_{\text{DD}}$or −40 to 100°C.$\text{FoM}_{\mathrm{S}, \text{DR}}$is 185.6 dB (10 kHz BW) and$>184 \text{dB}$(1-to-40kHz BW).