Low-Jitter PLL Design for Advanced Wireless CMOS Transceivers

To meet the ever-growing demand for higher throughput, advanced wireless technologies have deployed various techniques to boost data rates. Wi-Fi 7 operates across the 2.4-GHz, 5-GHz, and 6-GHz frequency bands, leveraging the higher bandwidth of the 6-GHz band to achieve ultrawide channels up to 320 MHz with 4K-quadrature amplitude modulation (QAM). For cellular applications, 3GPP 5G New Radio (NR) utilizes both sub-6-GHz and millimeter-wave (mm-wave) frequency bands to obtain 10+ Gb/s throughput. These techniques all demand local oscillators (LOs) that deliver state-of-the-art phase noise (PN) and spurious tone performance. This article reviews recent design trends and advanced circuit techniques for low-jitter fractional-N phase-locked loops (PLLs) for wireless applications. The review begins with the choice of PLL architecture and then moves on to the key analog circuit design techniques, focusing on low-jitter phase detectors (PDs) and low-PN voltage-controlled oscillators (VCOs). Digital calibration techniques are essential to maintain high performance across variations in process, voltage, and temperature (PVT). Thus, the article reviews their operational principles and advanced techniques. The article concludes with two LO chain design examples, for 5G frequency range 2 (FR2) cellular transceiver chipsets and a Wi-Fi 7 triple-band transceiver, respectively.