A 10T Soft-Error-Immune SRAM With Multi-Node Upset Recovery for Low-Power Space Applications

In this paper, a 10T Soft-Error-Immune SRAM (SIS10T) is proposed for space applications. To gauge the relative performance of SIS10T, it is compared with QUATRO10T, QUATRO12T, QUCCE12T, DICE12T and RHD12T. SIS10T can recover from single-event upsets of both polarities induced at all the sensitive nodes, as well as from single event multi-node upsets induced at its internal node-pair. Furthermore, SIS10T shows (consumes) a 1.66× (1.65×)/ 1.62× (1.35×)/ 1.46× (1.72×)/ 1.09× (2.06×) higher read stability (lower hold power) than QUATRO12T/ QUATRO10T/ QUCCE12T/ DICE12T @ VDD = 1 V. It also exhibits the highest write ability.