Package Warpage Reduction for Large CoWoS-R Packages

CoWoS-R platform provides low RC interconnect, good signal isolation and design scalability. This technology has been in production currently with good yield and reliability performance. CoWoS-R technology is designed to integrate $SoC$ and HBM together. For AI computing and Large Language Model (LLM) applications, more and more chiplets and HBMs are integrated to meet increasingly demands in high-speed computing requirements. The large size packages create significant challenges in warpage control for final testing and on-board assembly process and reliability. We built CoWoS-R packages with large interposer size of 5.5x TV consisting of 4 SOC + 12 HBMs and its corner split for window verification. The packages exhibit good process control in fine pitch ubump joining, flux clean, IPD bonding and underfill gap filling, and have good in-line yields. We can reduce the package warpage of this large form factor package $110\mathrm{x}110\text{mm}^2$ substrate. Analysis on various interposers and substrate sizes will be reported. The package reliability result with this new warpage reduction method will also be presented.