Mitigation of Single-Event Upset Sensitivity for 6T SRAM in a 0.18 μm DSOI Technology Considering High LET Heavy Ions Irradiation

This article concerns the top silicon layer thickness ( $T_{\text {SOI1}}$ ) and back-gate bias dependence of single event upset (SEU) cross section in $0.18 ~\mu \text{m}$ double-silicon-on-insulator (DSOI) static random access memory (SRAM) through high linear energy transfer (LET) heavy ions experiments. The experimental results show that the SEU cross section (SEU CS) increases as the LET rises. The thickness of the top silicon layer is a critical factor for SEU sensitivity in DSOI SRAM. The overall SEU CS for the SRAM with $T_{\text {SOI1}}$ = 65 nm was $\sim 32\times $ larger than that of the SRAM with $T_{\text {SOI1}}$ = 45 nm due to the reduction in collected charge. It is experimentally demonstrated that back-gate bias applied during heavy ion exposure strongly impacts SEU sensitivity. The 6T SRAM circuit exhibits exceptionally high tolerance to SEU by adjusting the back-gate bias. A back-gate biasing strategy is proposed in DSOI SRAM circuits which significantly lowers SEU sensitivity and power without performance loss. The physical mechanism of the effect of back-gate bias on SEU is explained through technology computer-aided design (TCAD) simulations, where the charge collection in a single transistor and the static noise margin in a 6T SRAM cell are analyzed. The 6T SRAM can mitigate SEU with LET value up to 118 MeV $\cdot $ cm2/mg. The proposed DSOI SRAM shows a highly reliable and low-power capability which is preferred in extreme radiation environment applications.