吞吐量
磁阻随机存取存储器
计算机科学
宏
随机存取
领域(数学)
数据保留
随机存取存储器
并行计算
操作系统
计算机硬件
无线
计算机安全
数学
纯数学
程序设计语言
作者
Tomoya Ogawa,Ken Matsubara,Yasuhiko Taito,Tomoya Saito,Masayuki Izuna,Koichi Takeda,Yoshinobu Kaneda,Takahiro Shimoi,Hidenori Mitani,Takashi Ito,Takashi Kono
标识
DOI:10.1109/isscc49657.2024.10454409
摘要
As the range of applications for industrial and ioT devices expands, such as with the integration of Al, higher-speed information processing will be desired for endpoint devices to reduce network latency and power consumption, due to network communication with the cloud. For sophisticated control and real-time processing, high-processing performance with GHz-class CPU clock frequencies and robust security is required in the crossover area located on the performance boundary between high-end microcontroller units (MCUs) and low-end microprocessor units (MPUs) [1]. One possible solution for such MCUs is to apply DVFS, which dynamically controls the supply voltage and the clock frequency depending on the processing load. In terms of process scaling, finer logic processes, 22 nm and beyond are being applied, but the development and manufacturing of embedded flash memories (eFlash) become more difficult and expensive [1]. For this reason, various types of emerging memories have been developed, and an embedded STT-MRAM (eMRAM) has begun to be used for mass production, since eMRAM has advantages such as high reliability and fast write speed compared to other emerging memories.
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