高电子迁移率晶体管
晶体管
异质结
蚀刻(微加工)
截止频率
材料科学
光电子学
电气工程
分析化学(期刊)
电压
纳米技术
化学
工程类
色谱法
图层(电子)
作者
Alexandr E. Shesterikov,Darya A. Shesterikova,Evgeniy V. Erofeev
标识
DOI:10.1109/apeie59731.2023.10347827
摘要
The paper presents an approach to the selection of the optimal heterostructure to ensure the specified parameters of HEMT. The parameters of four heterostructures with different parameters were analyzed in the framework of the study. Test transistor elements were fabricated on each of the heterostructures using 0.15 μm pHEMT process technology. The following parameters were measured: drain current per unit channel length at gate voltage equal to zero; maximum drain current per unit channel length; transistor cutoff voltage at drain current equal to 1 mA/mm; maximum transistor steepness value. As a result of analyzing the obtained data, a structure with carrier mobility in the channel of 5005 cm2/(V-s) and σ-doping concentration in AlGaAs of 1,31•10 12 cm -2 was selected. Also, a related task was to determine the optimal etching time of the gate recess. As a result of the analysis, the optimal etching time was 1.5 min. At this etching time, the greatest coincidence of transistor characteristics with the required values is ensured.
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