编译程序
计算机科学
微处理器
设计空间探索
过程(计算)
功率(物理)
补语(音乐)
平面布置图
计算机体系结构
优化编译器
电子设计自动化
微体系结构
功率优化
嵌入式系统
航程(航空)
功率消耗
程序设计语言
工程类
生物化学
物理
互补
量子力学
化学
航空航天工程
基因
表型
作者
David Brooks,Vivek Tiwari,Margaret Martonosi
标识
DOI:10.1145/339647.339657
摘要
Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.
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