中间层
材料科学
薄脆饼
制作
光电子学
生产线后端
基质(水族馆)
表征(材料科学)
硅
模具(集成电路)
电子工程
复合材料
纳米技术
图层(电子)
电介质
蚀刻(微加工)
医学
替代医学
海洋学
病理
工程类
地质学
作者
Vijay Sukumaran,Tapobrata Bandyopadhyay,Qiao Chen,Nitesh Kumbhat,Fuhan Liu,Raghuram V. Pucha,Yoichiro Sato,Mitsuru Watanabe,Kenji Kitaoka,Motoshi Ono,Yuya Suzuki,Choukri Karoui,Christian Nopper,Madhavan Swaminathan,Venky Sundaram,Rao Tummala
标识
DOI:10.1109/ectc.2011.5898571
摘要
This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.
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