A 12-bit 1-GS/s Current-Steering DAC With Paired Current Source Switching Background Mismatch Calibration

This article presents a spur-suppressed background calibration technique for high-speed current-steering digital-to-analog converters (DACs), based on a paired current source (CS) switching scheme. In conventional background calibration, periodic switching of CSs to and from the calibration mode introduces unwanted glitches that appear as spurious tones. The proposed technique introduces an intermediate common-state mode, where paired CSs steer equal and opposite currents to the differential output before entering or exiting calibration. This effectively cancels switching-induced glitches by common-mode (CM) rejection without compromising signal power or increasing noise. A 12-bit 1-GS/s DAC was fabricated in 28-nm FDSOI technology to validate the proposed method. Measurement results show that the proposed calibration achieves a spur-suppressed operation with an SFDR of 81-dBc near DC and greater than 70 dBc up to 286 MHz, with improved INL and DNL performance. The prototype DAC consumes 33 mW and achieves a figure of merit (FoMW,BW) of 28.4 fJ/conversion-step, demonstrating high linearity and power efficiency.