计算机科学
现场可编程门阵列
合成孔径雷达
延迟(音频)
核(代数)
自动目标识别
吞吐量
计算
嵌入式系统
人工智能
计算机硬件
无线
算法
数学
组合数学
电信
作者
Bingyi Zhang,Rajgopal Kannan,Viktor K. Prasanna,Carl Busart
标识
DOI:10.1109/hpec58863.2023.10363615
摘要
Synthetic Aperture Radar (SAR) automatic target recognition (ATR) is a key technique for remote-sensing image recognition. In real-world applications, massive SAR images are captured by airplanes or satellites, requiring high-throughput and low-latency processing. Recently, Graph Neural Networks (GNNs) have shown superior performance for SAR ATR in terms of accuracy and computational complexity. In this paper, we accelerate GNN-based SAR ATR on an FPGA. In the proposed design, we develop a customized data path and memory organization to execute various computation kernels of GNNs, including feature aggregation and feature transformation. We exploit the high bandwidth memory (HBM) of the FPGA to speed up data loading and store intermediate results. We employ the splitting kernel technique to improve the routability and frequency of the design on FPGA. We implement the proposed design using High-level Synthesis (HLS) on a state-of-the-art data-center FPGA board, the AMDlXilinx Alveo U280. Compared with implementations on state-of-the-art CPUs (GPUs), our FPGA implementation achieves a 5.2x (l.57x) lower latency, a lOx (3.3x) higher throughput, and is 36.2x (7.35x) more energy efficient.
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