Impact of negative gate stress on the reliability of p-GaN gate HEMT devices under dynamic switching operation

Abstract In this study, we investigated the impact of single stress (negative gate bias stress) and combined stress (both negative gate bias stress and drain voltage stress) on the instability of the threshold voltage (V TH ) on p-GaN gate HEMT devices during dynamic switching operation. The dynamic V TH shift during pulsed negative gate bias stress was investigated for the first time. The V TH exhibits an initial rapid increase upon the initiation of stress and a slight decrease with increasing stress time. For the applied stresses of V GS = −1/−2/−3 V, the V TH shift values were, respectively, 0.12/0.16/0.19 V at the stress time of 100 s. Under the stress of V GS = −3 V and V DS = 100 V, the shift value of V TH was 0.61 V. After the combined stress, the saturation and off-state leakage currents exhibited a significant reduction, with the latter decreasing by one order of magnitude after the reverse voltage stress. When only a negative gate bias stress is applied, the degradation of the device can recover quickly after the stress is removed. In contrast, the positive shift in V TH caused by the drain-voltage stress is difficult to recover. Furthermore, the mechanisms underlying the V TH shift mentioned above were explored. Under single-stress conditions, the shift in V TH is associated with shallow traps that trap electrons. Meanwhile, under the combined stress, the degradation of Vth was also affected by the deep-level traps.