SEM overlay target design optimization by e-beam simulation

As CMOS node advanced, device patterns become smaller and denser, which as a result, decrease overlay budget. Each contributor to overlay error is significant and should be minimized, even at early stage of technology development. The performance of optical overlay metrology is challenged by the difference between optical target and device structure, which response differently to lithography optics (aberration response), hence reduce correlation to device overlay. E-Beam overlay can mitigate this gap as it can measure device-size structures. In this case, the challenge is to measure small, dense and buried patterns, which may have low visibility (contrast and edge resolution), but still provide acceptable total measurement uncertainty (TMU) to reduce error budget from the tight overlay specs. Finding optimal target where its design is similar or close to device and is measurable with robust performance, without designing and re-design targets in multiple tape-out cycles, can be done by simulating scanning electron microscopy (SEM) measurements of different device-like targets and find the optimal point where predicted performances are good and the design is as close to the device. In this paper we propose a method that evaluates measurement performances of different SEM overlay target designs using e-Beam simulation of back-scatter electrons (BSE) yield from buried layers. Targets with different design rules: pitch, critical dimensions (CD) and edge-to-edge distance are simulated at different measurement conditions and results are compared to measurement of actual targets on wafer. The comparison shows that measurement performance can be predicted by simulation, which can point out optimal target design and measurement conditions.