An area efficient design methodology for SEU tolerant digital circuits

This paper presents a new circuit design style for radiation hardened digital circuits. The proposed design methodology is based on the well known DCVSL circuit style. The original DCVSL has been modified to build in robustness against single event upsets due to particle strikes. The paper presents simulation results for logic gates and arithmetic circuits built using the proposed design scheme. The circuits were found to have area savings of about 26% over their static CMOS counterparts at the cost of 7% extra delay. The design style described in this paper was found to be extremely reliable with 100% SEU mitigation for a wide spectrum of charge and current profiles at relatively lower cost than previously published circuit schemes for SEU mitigation.