Gate-to-channel shorts in BiCMOS logic gates

This paper describes the effects of gate-to-channel breakdown on the operation of BiCMOS logic gates. Both the static and dynamic behaviours of the gates are examined. The influence of the position of the defect within the channel is noted. Expressions for the logic levels and the quiescent current of an inverter in the presence of defects are calculated as an example. SPICE simulations confirmed the results and were used with other logic gates. The experimental results show that gate-to-channel breakdown cannot be modeled by a stuck-at fault. I/sub ddq/ testing is more effective than delay testing in detecting these effects. Test patterns for I/sub ddq/ are given.>