Less-Conservative Current Feasible Region for PLL-Synchronized VSCs Considering Variable Damping Under Asymmetric Faults

During low voltage ride through (LVRT) period, variable damping significantly affects the transient synchronous stability (TSS) of phase-locked loop-synchronized voltage-source converters (PLL-VSCs). However, in previous studies on TSS analysis under asymmetric faults, completely ignoring and insufficiently considering variable damping both increase the misjudging risk or yielding conservative estimation results. To fill this gap, this paper proposes an improved equal area criterion (iEAC) considering variable damping to qualitatively analyze the TSS of PLL-VSC and quantitatively estimate the lessconservatism current feasible region under asymmetric faults. Firstly, the sequence-domain transient synchronization model with PLL dynamics is developed to reveal the synchronization characteristics of PLL-VSC. Then, an improved equal area criterion considering variable damping is proposed to qualitatively analyze the effect of variable damping on TSS. Compared to traditional methods, the proposed iEAC improves both accuracy and conservatism on TSS analysis. Moreover, an iterative estimation method based on the iEAC is put forward to construct a less-conservatism sequence-domain current feasible region (SCFR), which provides a quantitative design for current injections under asymmetric faults to achieve system LVRT. The expansion feasibility of the proposed modeling and TSS analysis method to the multi-VSCs system is fully discussed. Finally, hardware-in-loop experiments validate the effectiveness and superiority of the theoretical analysis.