作者
Gaurav Thareja,Ashish Pal,Xingye Wang,S. Dağ,Shi You,Shashank Sharma,Qing Zhu,Carmen Leal Cervantes,Shinjae Hwang,Matthew Spuller,Ben Ng,P. Sathish Kumar,Norman Tam,Max Gage,Sameer Deshpande,Zhiyuan Wu,Alexander Jansen,Liton Dey,Feng Chen,Xian-Jin Xie,Keyvan Kashefizadeh,V H Prasad Reddy,Andy Y. H. Lo,Zhebo Chen,Sidney Huey,Jianshe Tang,Ren He,Mehul Naik,Brian J. Brown,Sree Kesapragada,Buvna Ayyagari- Sangamali,El Mehdi Bazizi,Xianmin Tang
摘要
We present novel back-end-of-line (BEOL) copper interconnect integration for advanced technology nodes using integrated selective barrier copper barrier seed (CuBS) process, annealing and chemical mechanical planarization (CMP). Electrical tests (resistance, reliability) combined with Materials-to-Systems Co-Optimization (MSCO™) simulations confirm significant power-performance-area (PPA) gains for 3nm technology node and beyond.
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