CMOS芯片
微电子
计算机科学
电子工程
纳米电子学
重点(电信)
电气工程
功率消耗
逻辑门
工程类
纳米技术
功率(物理)
材料科学
物理
量子力学
作者
H.‐S. Philip Wong,D.J. Frank,P. M. Solomon,C. Wann,J.J. Welser
出处
期刊:Proceedings of the IEEE
[Institute of Electrical and Electronics Engineers]
日期:1999-04-01
卷期号:87 (4): 537-570
被引量:432
摘要
This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.
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