The Packaging Technology of CMOS Image Sensors: A Review

包装工程 可靠性(半导体) 集成电路封装 炸薯条 CMOS芯片 电子包装 材料科学 芯片级封装 温度循环 倒装芯片 光刻胶 汽车工程 薄脆饼 晶圆级封装 机械工程 表面贴装技术 引线键合 过程(计算) 耐久性 电气工程 工程类 瓶颈 图像传感器 汽车工业 试验夹具 嵌入式系统 材料选择 真空包装 热铜柱凸点 电子工程 计算机科学 模具(集成电路) 透射率
作者
Jikang Liu,Yue Wang
出处
期刊:ACS applied electronic materials [American Chemical Society]
卷期号:8 (9): 3762-3786
标识
DOI:10.1021/acsaelm.6c00434
摘要

The CMOS image sensor (CIS) has been widely used in multiple fields such as smartphones, automotive electronics, security monitoring, and medical imaging. According to the structure, the CIS has usually been classified into front-side illumination (FSI) CIS, back-side illuminated (BSI) CIS, and stacked BSI CIS. The wafer-level packaging (WLP) technology based on the through-silicon via (TSV) for CIS chips mainly includes the laser drilling process, the flat stay process, and the ultrathin process, which have been developed by several outsourced semiconductor assembly and testing (OSAT) companies including SONY, Samsung Electronics, TSMC, Huatian Technology, and so on. Meanwhile, other advanced CIS packaging technologies including hybrid bonding, wafer-level stacking, and optical packaging technology have also been developed to meet the requirements of CIS chip packaging. The core pain points of CIS chip packaging including wafer warpage, thermal management, moisture reliability, and optical stray light also exist to prevent the development of CIS chip packaging. During the packaging process of CIS wafers, organic materials mainly including a cavity wall photoresist, high temperature bonding adhesive, printing ink, high transmittance adhesive, and photoresist were applied. The reliability testing of packaged CIS chips, including precon (including bake, soak, and reflow), high-temperature storage test (HTST), low-temperature storage test (LTST), temperature cycle test (TCT), and other tests, was performed to evaluate the reliability and durability of packaged chips by simulating various environmental conditions and stresses. Finally, the core challenges faced by technological upgrades for CMOS technology mainly included the physical limit approaching, the bottleneck of material system innovation, and the challenge of balancing performance and power consumption. The potential risks of CMOS technology in the field of security mainly included hardware-level vulnerabilities, security threats of the supply chain, and data security risks.
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