Fabrication of 1700 V SiC MOSFETs with optimized JFET region and current spreading layer

Abstract This paper reports the simulation, fabrication and characterization of high current density 1700V SiC MOSFETs with a hexagonal cell layout. A novel SiC MOSFET structure incorporating step-type implantation in both the JFET region and the current spreading layer (CSL) (JC-MOS) is developed to address the high resistance issues in these regions. A remarkable decrease in the on-resistance ( R on) of 20.2% is realized through optimized implantation conditions. An ultra-low R on of 15 mΩ and a specific on-resistance ( R on,sp ) of 3.75 mΩ·cm 2 are achieved, both of which are the lowest reported values for 1700 V SiC planar MOSFET devices to date. By reducing the JFET region width from 1.2 μm to 0.9 μm, the JC-MOS device feedback capacitance ( C rss ) and the high-frequency figure of merit (HF-FOM, defined as R on,sp × specific gate-drain charge ( Q gd,sp )) is reduced by 44.6% and 43.1%, respectively, while simultaneously increasing the avalanche energy ( E av ) from 3.42 J to 4.25 J. Furthermore, the dependence of the JFET and CSL doping concentration on breakdown voltage ( BV ), avalanche tolerance and maximum electric field of the gate-oxide layer ( E ox ) is analyzed using experimental and simulation results.