Fabrication of 1700 V SiC MOSFETs with optimized JFET region and current spreading layer

Abstract In this paper, the simulation, fabrication and characterization of high current density 1700V SiC MOSFETs with a hexagonal cell layout are reported. A novel SiC MOSFET structure incorporating step-type implantation in both the JFET region and CSL (JC-MOS) is developed to address the high resistance issues . Through optimized implantation conditions, a remarkable decrease in the Ron of 20.2% is realized. An ultra-low Ron of 15mΩ and a Ron,sp of 3.75mΩ·cm2 are achieved both of which are the lowest reported values for 1700 V SiC planar MOSFET devices to date. By reducing the JFET region width from 1.2μm to 0.9μm, the JC-MOS device Crss and the HF-FOM are reduced by 44.6% and 43.1%, respectively, while simultaneously increasing the Eav from 3.42J to 4.25J. Furthermore, the dependence of the JFET and CSL doping concentration on BV, avalanche tolerance and maximum Eox is analyzed using experimental and simulation results.