Aligned carbon nanotube integrated circuit downsizing toward a sub-10 nm node

Abstract Transistors on aligned semiconducting carbon nanotubes (A-CNTs) have been considered a promising substitute for mainstream Si transistors to extend integrated circuit (IC) technology owing to their potential advantages of easy miniaturization and high energy efficiency, but whether A-CNT FETs can be scalably fabricated with ultrascaled whole dimensions while maintaining high performance remains questionable. Here, we explore the whole size scaling down potential of A-CNT transistors and demonstrate the possibility of implementing such small-geometry transistors in ultra-large-scale ICs that consist of billions of transistors. A-CNT transistors with a contacted gate pitch (CGP) of 175 nm have been achieved by simultaneously scaling the gate length and the contact length, and exhibit an on-current of 2.24 mA/μm and a peak transconductance of 1.64 mS/μm, surpassing silicon 45 nm node transistors in terms of both size and electronic performance. A static random-access memory (SRAM) cell has been built using six A-CNT transistors in an area of 0.967 μm2, which is comparable to the commercial silicon 90 nm technology node and is the smallest SRAM cell based on non-Si semiconductors. Furthermore, a full-contact structure is introduced between the metal and A-CNTs to achieve a contact resistance as low as 90 Ω·μm and to reduce the dependence on the contact length. A-CNT transistors downsized to a CGP of 55 nm (corresponding to the silicon 10 nm technology node) have been demonstrated to outperform 10 nm Si MOS transistors in terms of carrier mobility and Fermi velocity, indicating the tremendous potential of A-CNT transistors in high-performance digital ICs of sub 10 nm nodes.