A low in-band phase noise Fractional-N ADPLL based on Switched-Capacitor-DPI

This paper presents a fractional-N all digital phase locked loop (ADPLL) based on a low in-band phase noise switched-capacitor digital phase interpolator (SC-DPI), which reduced the in-band phase noise of ADPLL. The SC-DPI utilized a capacitance vector-sum structure with a short signal chain to improve the in-band phase noise performance. Designed in 40-nm CMOS technology, from simulation results, the proposed SC-DPI worked at 1GHz and achieved -126.2 dBc/Hz in-band phase noise at 1kHz and -142.6 dBc/Hz at 1MHz. The proposed 8GHz ADPLL based on SC-DPI achieved -110.5 dBc/Hz and -117.2 dBc/Hz in-band phase noise at 1kHz and 10kHz respectively.