铜互连
电介质
材料科学
低介电常数
薄脆饼
高-κ电介质
多孔性
钴
毯子
抵抗
纳米技术
光电子学
复合材料
冶金
图层(电子)
作者
L. Zhang,Jean‐François de Marneffe,N. Heylen,Gayle Murdoch,Zsolt Tökei,Juergen Boemmels,Stefan De Gendt,Mikhaı̈l R. Baklanov
摘要
Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm ½ pitch Meander-Fork structure, leading to keff below 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.
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