Next-Generation High-Density PCB Development by Fan-Out RDL Technology

High-density interconnect (HDI) printed circuit boards (PCBs) are in high demand for smartphones, particularly those with fifth generation (5G) functionality, due to their smaller form factors, higher interconnection densities, and improved integrative ability. Various advanced PCB technologies are available, including HDI PCBs and substrate-like PCBs (SLPs). However, even for substrate-like PCBs, the line width (L) and spacing (S) of the copper traces are limited to$25~\mu \text{m} / 25~\mu \text{m}$, and fine-line development also faces yield and cost challenges. Accordingly, the present study utilizes an redistribution layer (RDL) first fabrication process to develop a fine line width/spacing ($10~\mu \text{m} / 10~\mu \text{m}$) Fan-out interposer (FOI) on PCB architecture with a higher I/O (Input/Output) density, greater yield, and lower cost. A three-dimensional (3D) ANSYS finite element (FE) model combined with volume fractions approach applied to equivalent thermomechanical properties of the multilayer RDL is introduced. The validity of the simulation model is confirmed by comparing the numerical results for the out-of-plane deformation of the top surface of the FOI with the experimental observations. Then, the effects of five design parameters on the warpage and solder joint stress performance of the FOI-PCB architecture are identified through parametric analysis. Finally, a second-order response surface methodology (RSM) model and Box-Wilson central composite design (CCD) method are employed to examine the interactive effects of the structural design factors of the FOI-PCB architecture on the FOI warpage under typical manufacturing thermal loading conditions. It is shown that a smaller overall size of the FOI is beneficial in reducing the warpage by minimizing the coefficient of temperature expansion (CTE) mismatch between the interposer and the PCB.