Supercarrier Redistribution Layers to Realize Ultra Large 2.5D Wafer Scale Packaging by CoWoS

Interposer based 2.5D systems have gained popularity to integrate chips and chiplets of advanced logic and stacked memory of high bandwidth memory (HBM) for performance-oriented artificial intelligence (AI) high performance computing (HPC) systems. The size of the interposer is one of the key indices for this technology. At a given transistor density, a larger interposer area means the capacity to carry a higher number of transistors within a package, which directly contribute to the overall performance gain for technology advancement. In this paper, we propose and demonstrate a new CoWoS interposer structure to realize an unprecedented interposer area of $\sim 4000\text{mm}^{2}$ . This is achieved by a multiple layers of supercarrier redistribution layers (SC-RDL) at the backside of LSI (local Si interconnect) interposer of CoWoS-L. The SC-RDL's fan out to an area the same as the organic substrate so that the key technology challenges associated with interposer at this size range are greatly mitigated. These include the difficulty of oS (on substrate) assembly, C4 bump pitch scaling, package reliability margin, and high package coplanarity issues. The structure has been demonstrated on mechanical samples of a 91 mm $\mathrm{x} \ 91$ mm package. Excellent package coplanarity and structure stability as checked by multi-reflow are reported. It also holds the potential to simplify the routing layers in the organic substrate by fanning out the IO's to cover the entire substrate. In addition to achieving the interposer dimension scaling continuously, the SC-RDL based CoWoS-L with the extended area also promises to accommodate more embedded passives and optical engines required in a CPO (co-packaged optics) structure.