Application of Machine Learning Techniques to Characterize Floating Point Benchmarks using Hardware Events

The pursuit of improved computing architecture drives continuous innovation to enhance user application performance. One such advancement involves the implementation of floating-point accelerators. However, identifying applications heavily reliant on floating-point operations proves complex due to application intricacies. Selecting optimal workloads for execution on floating-point accelerators can yield significant benefits, including up to a 30% reduction in execution time. In this article, the authors propose a novel approach that leverages machine learning algorithms and meticulous analysis to identify the minimum hardware performance counters necessary for detecting applications with significant utilization of floating-point operations. Our methodology achieves an accuracy of 69% using unsupervised machine learning and 100% using supervised machine learning. By focusing on workloads that stress new CPU designs, this approach streamlines the development and validation of novel computing architectures. It effectively pinpoints ideal candidates for benchmarking new floating-point co-processors, optimizes test execution time, and minimizes power consumption during the validation phase. This research promises to drive advancements in computing architecture, leading to improved application performance and efficiency.