EIA/TIA-485 transceiver in standard 130 nm CMOS technology

This paper describes the design of the transceiver, which is the implementation of the physical layer of EIA/TIA-485 standard. This circuit is a part of a more complex System on Chip designed in 130 nm CMOS technology. The problems encountered during the design process was described. The crucial issue was the relatively high voltage range, from -7 V to 12 V, that may appear on the pins of the SoC and damage it. The circuit techniques was proposed to solve this problem and in the result the complete solution of the transceiver, consisting of a driver and a receiver is presented. The transceiver uses standard 3.3 V IO transistors. The simulation results show that designed transceiver comply with the standard.