Across-Array Coding for Resistive Memories With Sneak-Path Interference and Lognormal Distributed Resistance Variations

Resistive random-access memory (ReRAM) is a promising non-volatile memory technology for achieving high-density and high-speed data storage. However, its crossbar array structure leads to a severe problem known as the sneak path interference (SPI), which is data dependent and correlated within a memory array. Meanwhile, variations of the memory fabrication process also cause deviation of memory cell resistances from their nominal values, which typically follows the lognormal distribution. In this letter, we first propose a cascaded channel model that incorporates these two key factors that affect the reliability of ReRAM. By analyzing the channel correlation of ReRAM caused by the SPI, we develop a novel scheme to estimate the probability of each memory cell to be affected by the SPI, based on which the log-likelihood ratio (LLR) of each channel bit can be generated. Moreover, we propose a novel two-step across-array bit allocation scheme, which distributes the low-density parity-check (LDPC) codewords to multiple memory arrays so as to minimize the correlation of the channel coded bits for decoding. Simulation results show that the proposed across-array bit allocation scheme with LDPC coding can achieve significantly better error rate performance than the prior art coding schemes, with similar implementation complexity and latency.