The noise and linearity optimization for a 1.9-GHz CMOS low noise amplifier

For radio frequency integrated circuits (RFICs), and especially for low noise amplifiers (LNAs), noise and linearity performances are critical characteristics. A detailed analysis of noise and linearity for the cascode architecture, a widely used circuit structure in LNA designs, is presented in this paper. The noise and the linearity improvement techniques for cascode structures are also developed and have been proven by computer simulation experiments. Both the theoretical analysis and the simulation results show that, for LNAs with the cascode structure, the first MOSFET dominates the noise performances of the LNA, while the second MOSFET contributes more to the linearities. A conclusion is thus obtained that the first and second MOSFET of the LNA can be designed to optimize the noise performance and the linearity performance separately, without trade-offs. 1.9 GHz CMOS LNA simulation results are also given as an application of the developed theory.